1 Contents
(a) Introduction to IC
（b）Digital IC design process
（c）VerilogIntroduction
（d）VivadoComprehensive strategy three and four
(e) End
1 Introduction to IC
(a) In IC design, designers use circuit design tools (such as EDA software) to design and simulate various circuits, such as logic circuits, analog circuits, digital signal processing circuits, etc. Then, according to the specifications and requirements of the design circuit, layout design and wiring are carried out to determine the position and wiring method of each circuit component. Finally, physical design is carried out to consider issues such as electromagnetic compatibility, power consumption optimization, timing, etc., and mask information required for chip manufacturing is generated.
(b) IC design is the core part of chip design. It involves multiple levels such as circuit design, layout design, physical design, etc., and aims to integrate various functional circuits into a small chip to achieve highly integrated and highperformanceand low power consumption target.
2 Digital IC design process
(a) Specification definition: Define the chip's functional specifications, performance indicators and interface requirements according to application requirements.
(b) Architecture design: design the overall structure of the chip, including the division and organization of modules such as signal processing, control logic and storage.
(c) RTL design: usehardwareDescription languages (such as Verilog or VHDL) convert the chip's functionality into RTL (Register Transfer Level) level code. RTL design includes logic design and functional simulation.
(d) Comprehensive and optimization: Comprehensive RTL code into gate-level circuit netlists and optimize to meet performance, power consumption and area indicators.
(e) Layout and wiring: Layout design is carried out according to the optimized circuit netlist, including the relative positions and dimensions of each circuit module, and then wiring is carried out to determine the path of the circuit connection.
(f) Physical verification: Perform physical verification such as electrical rule checking (DRC, Design Rule Checking) and layout criteria checking (LVS, Layout Versus Schematic) to ensure that the chip layout meets manufacturing requirements and design specifications.
(g) Static timing analysis: Perform static timing analysis on the chip, including timing path constraint settings, clock domain division and timing convergence verification, etc., to ensure that the timing requirements are met.
(h) Dynamic simulation: perform functional simulation and timing simulation of the chip to verify the correctness of the design and performance indicators.
(i) Special test integration: Design test circuits and test interfaces with integrated chips for subsequent chip testing and troubleshooting.
(j) Layout design: Generate the layout design of the chip, including the planning of the metal wire layer, the setting of design rules, etc.
(k) Simulation and verification: Simulation and verification of the analog circuits in the design to ensure their performance and stability.
(m) Chip processing and manufacturing: Submit the designed chip layout to the chip manufacturer for chip manufacturing and packaging.
3 Introduction to Verilog
(a) Verilog HDL is a hardware description language that describes the structure and behavior of digital system hardware in text form. It can represent logical circuit diagrams, logical expressions, and also represent the logical functions completed by digital logic systems.
(b) Verilog HDL and VHDL are the two most popular hardware description languages in the world, both developed in the mid-1980s. The former isGatewayDesign Automation (which was acquired by Cadence in 1989). Both HDLs are IEEE standard.
(c) Verilog HDL is a hardware description language used toalgorithmDigital system modeling at various abstract design levels from level, gate to switch.
4 Vivado comprehensive strategy three and four
Q34: Vivado implements strategy three and four
A34-1：CARRY_REMAP；
(1) This option can remap individual CARRY* units into lookup tables (LUTs) to improve the wiring results of the design.
(2) When using the -carry_remap option, only single-stage carry chains will be converted to LUTs.
(3) The CARRY_REMAP attribute can specify a longer carry chain to be converted during optimization.
(4) CARRY_REMAP attribute
• CARRY_REMAP=0: No remapping is performed.
• CARRY_REMAP=1: Remap individual CARRY units that do not belong to the carry chain.
• CARRY_REMAP=2: Remap carry chains with length 2 or shorter.
（a）set_property CARRY_REMAP <value> <objects>
（b）set_property CARRY_REMAP 2 [get_cells -hier -filter {ref_name == CARRY8}]
Note: Reduce wiring pressure and increase LUT delay;
5 End
(a) I hope reading the author’s blog can be helpful to you;
(b) I hope readers can learn IC quickly orFPGAThis technology;
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