A new instruction set architecture, RISC-V.

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Introduction to the RISC-V Instruction Set Architecture

Universal Register Model

RISC-V privilege class

RISC-V Instruction Set Description

RISC-V Summary

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Introduction to the RISC-V Instruction Set Architecture

RISC-V (pronounced "risk-five") is a new instruction-set architecture that was originally developed by the U.S.University of California, Berkeleyof the EECS sectorComputer Science SectorIt was invented in 2010 by developers including Prof. Krste Asanovic, Andrew Waterman and Yunsup Lee. The "RISC" stands for Reduced Instruction Set, and the "V" stands for "V", which Berkeley has taken from RISC.IStarted designing the fifth generation of the instruction set.

In 2010, a team of researchers from the University of California, Berkeley, analyzed theARM、MIPS、SPARC、X86and many other instruction sets, it was found that these instruction sets are not only increasing in complexity, but also have aintellectual property rights (law)risk, and there is no direct correlation between the type of processor architecture and processing power. To address the above issues, the group designed and launched a free and open instruction set architecture RISC-V based on the BSD protocol license, and its prototype chip was also successfully flowed in January 2013.The RISC-V instruction set is characterized by superior performance and is completely free and open.The design goal of RSIC-V is to be able to meet the needs of processors of various levels of complexity, ranging from microcontrollers to supercomputers, and to support a variety of implementations ranging from FPGAs, ASICs, and even future devices, as well as to be able to efficiently implement a wide range of microarchitectures, support a large number of customization and acceleration features, and be well adapted to existing software and programming languages.The RISC-V industry ecosystem is entering a period of rapid development.UC Berkeley established the RISC-V Foundation, a non-profit organization, in 2015, which aims to aggregate global innovation forces to jointly build an open, collaborative hardware and software community and create a RISC-V ecosystem. Over the past three years, Google, Qualcomm, IBM, NVIDIA, NXP,,Western Digital Corporation (WDC), Microsemi, and the Institute of Computing, Chinese Academy of Sciences,Massachusetts Institute of Technology (MIT), University of Washington,United Kingdom of Great Britain and Northern IrelandMore than 100 companies and research organizations, including Aerospace Systems, have joined the RISC-V Foundation.

The RISC-V Foundation maintains the RSIC-V instruction set standards manual and architecture documentation, and each year the RISC-V Foundation organizes a variety of symposiums and global events to bring the broad ecosystem together to discuss current and future RISC-V projects and implementations in order to promote communication and development in the RISC-V camp. The success of an instruction set architecture is heavily dependent on the software ecosystem. Currently available RISC-V software tools includeGNU Compiler Collection(GCC toolchain, GDB debugger).LLVMtoolchain.OVPsimemulator (and the RISC-V fast processor model library).SpikeEmulator andQEMUsimulators. Current operating systems that support this instruction set architecture include FreeRTOS,SylixOS、RT-Thread, Linux, etc.The RTRISC-V architecture can't shake the x86 and ARM architectures in a short period of time, but with more and more companies and projects adopting RSIC-V architecture processors, it is believed that the software ecosystem of RSIC-V will gradually grow.

Universal Register Model

RISC-V has 32integer (math.)processor registerx0~x31which31 general-purpose registers x1 to x31, which hold integer values, and register x0, which is a constant 0 for hardware concatenation.When implementing floating point extensions specifically 32floating pointprocessor registerf0~f31。For RV32, its x registers are 32 bits wide, and for RV64, they are 64 bits wide.

where the RISC-V register call conventionBelow:

The RISC-V calling convention passes arguments in registers whenever possible, and up to eight integer registers, a0-a7, and up to eight floating-point registers, fa0-fa7, are used for this purpose. The return value of a function is stored in integer registers a0 and a1, and in floating-point registers fa0 and fa1. Structures with one or two floating-point values are returned in the floating-point registers, while other return values can be placed in a0 and a1. Larger return values are returned entirely in memory, and the caller allocates these memory areas and passes them to the callee as the first hidden parameter. In the standard RISC-V calling convention, the stack grows down and the stack pointer is always aligned to 16 bytes.

In addition to the parameter registers and return value registers, the 7 integer registers t0-t6 and the 12 floating-point registers ft0-ft11 are temporary registers that are destroyed during the call and must be saved in the caller if they are to be used later. the 12 integer registers s0-s11 and the 12 floating-point registers fs0-fs11 are left unchanged after the call and must be saved in the callee if they are to be used later. The 12 integer registers s0-s11 and the 12 floating-point registers fs0-fs11 are kept unchanged after the call.

RISC-V privilege class

RISC-V defines four privilege level modes. The different privilege levels contain multiple CSR (control and status register) registers. The four privilege level information is shown in Table 1.1 below:

Privilege levels are used to provide protection between different software stack components, and attempting to perform an operation that is not allowed by the current privilege mode will result in an exception being thrown. The machine level is the highest level of privilege and is the only required privilege level for the RISC-V hardware platform. Code running in machine mode (M-mode) is inherently trustworthy because it has access to the machine implementation at a low level. User mode (U-mode) and Administrator mode (S-mode) are used for legacy applications and operating systems, respectively, while Hypervisor mode (H-mode) is intended to support virtual machine monitors.

All hardware implementations must provide M-mode, as this is the only mode that provides unrestricted access to the entire machine. The simplest RISC-V implementations can provide only M-mode, although this does not provide protection against incorrect, malicious application code. Many RISC-V implementations also support at least one user-mode (U-mode) to protect the rest of the system from being corrupted by application code.

The standard RISC-V ISA sets up a 12-bit encoding space (csr[11:0]) that can be used for 4096 CSRs. by convention, the high 4 bits of the CSR address (csr[11:8]) are used to encode the read/write accessibility of the CSR based on privilege level. The top 2 bits (csr[11:10]) indicate whether this register is readable/writable (00, 01, or 10) or read-only (11). The next 2 bits (csr[9:8]) indicate the lowest privilege level required to be able to access this CSR (00 for user level, 01 for administrator level).

Attempting to access a CSR that does not exist will generate an illegal instruction exception. Attempting to access a CSR that does not have the appropriate privileges or to write a read-only register will also generate an illegal instruction exception. A read/write to a register may contain bits that are read-only, in which case writing the read-only bits is ignored.

Descriptions of CSR-related registers can be found in the Privileged Level Instruction Manual, where the machine mode registers are shown below:

The assembly language pseudo-instruction CSRR rd, csr for reading a CSR is encoded as CSRRS rd, csr, x0. The assembly language pseudo-instruction CSRW csr, rs1 for writing a CSR is encoded as CSRRW x0, csr, rs1, and the pseudo-instruction CSRWI csr, zimm is encoded as CSRRWI x0, csr, zimm.

RISC-V Instruction Set Description

RISC-V is designed to support rich customization and specialization. The basic integer ISA can be enhanced by one or more optional instruction set extensions, but the basic integer instruction set cannot be redefined. We categorize RISC-V instruction set extensions into standard and non-standard extensions. Standard extensions are generally useful and do not conflict with other standard extensions. Non-standard extensions are highly specialized and may conflict with other standard or non-standard extensions. Instruction set extensions may have slight functional differences depending on the width of the basic integer instruction set.RISC-V has developed a naming convention for basic instructions and instruction set extensions with the command convention shown below.

To support more general software development, a set of standard extensions have been defined to provide multiplication/division,atomic operationand single- and double-precision floating-point arithmetic. The basic integer ISA is named "I" (prefixed with RV32 or RV64 depending on the width of the integer registers), which contains the integer compute instructions, integer load, integer store, and control flow instructions, and is required in all RISC-V implementations. The standard integer multiply and divide extension, named "M", adds instructions for multiplying and dividing values stored in integer registers. The standard atomic instruction extension, named "A", adds instructions to perform atomic read, modify, and write operations on memory to support interprocessor synchronization. The standard single-precision floating-point extension, named "F", adds floating-point registers, single-precision compute instructions, and single-precision load and store instructions. The standard double-precision floating-point extension, named "D", extends the floating-point registers and adds double-precision compute instructions, load and store instructions. A basic integer kernel with these four standard extensions ("IMAFD"), abbreviated as "G", provides a general purpose scalar instruction set, and the RV32G and RV64G are now the default target machines for our compiler toolchain. The following diagram depicts these and other planned standard RISC-V extensions.

The base RISC-V ISA has 32-bit fixed-length instructions and must be aligned on 32-bit boundaries. However, the standard RISC-V coding model is designed to support an extension for variable-length instructions, where each instruction length can be an integer multiple of the length of a 16-bit instruction wrapper, and these instruction wrappers must be aligned on 16-bit boundaries. The standard compressed ISA extension, by providing compressed 16-bit instructions, reduces code size and relaxes alignment requirements to allow all instructions (16-bit and 32-bit) to be aligned to any 16-bit boundary to increase code density.

Standard RISC-V instruction length encoding conventions. All 32-bit instructions in the base ISA have the lowest 2 bits set to 11. Instructions in the optional compressed 16-bit instruction set extensions have the lowest 2 bits set to 00, 01, or 10. Standard instruction set extensions longer than 32-bit have additional bits set to 1 in the lower bits, and the 48-bit and 64-bit length conventions are shown in Figure 1.1. Instruction length information between 80 and 176 bits is encoded in a 3-bit field [14:12], giving the number of 16-bit words, plus the first 5 x 16-bit words. Bits [14:12] are encoded as 111, reserved for encoding longer instructions in the future.

In the basic ISA, there are four core instruction formats (R/I/S/U), as shown in Figure 2.2. All instructions are fixed 32-bit length and must be aligned on 4-byte boundaries in memory. When a conditional branch or unconditional transfer occurs and the destination address is not aligned to a 4-byte boundary, an instruction address misalignment exception is thrown. If the conditional branch is not taken, then a fetch-index misalignment exception will not be thrown.

In all formats, RISC-V fixes the source registers (rs1 and rs2) and the destination register (rd) in the same location to simplify instruction decoding. In the instructions, the immediate numbers are packed towards the leftmost available bit and are allocated to minimize hardware complexity. Specifically, the sign bit for all immediate numbers is always in bit 31 of the instruction to speed up the sign expansion circuitry.

General operating system bottom developers are involved in writing assembly code, and generally use the compiler to provide pseudo-instructions for programming, RISC-V pseudo-instructions supported by the following chart. Mastery of the following pseudo-instructions has been sufficient to meet the assembly programmer to write assembly code.

Table 21.2 RSIC-V CSR pseudo-instructions

RISC-V Summary

The open and free RISC-V architecture has attracted a large number of well-known domestic and foreign enterprises, research institutes and startups to develop processors based on the RISC-V instruction set architecture, including Google and HP,Oracleand Western Digital, etc. Currently, China is still in the initial stage, many domestic research institutions and startups are based on some open-source RISC-V IP cores or SiFive's open-source SOC to do incremental development.

Yuanfeng, as a member of this group, is committed to building an ecosystem of RISC-V embedded real-time operating systems and their development environments, and its current major efforts arePorting FreeRTOSThe system is operated on SiFive's HiFive1 development board and the supporting development environment is provided. The development environment provides basic compiling, running and debugging environments, including OpenOCD, Jlink and other hardware debugging environments, and provides FreeRTOS operating system project for users to develop FreeRTOS applications. Subsequently will also supportRT-Thread、SylixOS and other operating systems and integrated into the development environment, easy to use for development and debugging.

The following will be written <<RISC-V development environment based on the HiFive1 development board to build >> and << how to put theFreeRTOSOS porting to RISC-V architecture>>.