ARM Learning (29) NXP Dual Core MCU MCXN94 Learning

The author to introduceNXP Dual core board , new series mcxn94

1. Introduction to the new MCX series

NXPMCU The Kinetis and LPC series, the RT series, and now the MCX series, which consists of four series, and the MCX N series, which has already been released, are all part of the MCX family.

• MCX N SeriesThe company's high-performance microcontrollers, edge-secure smart microcontrollers, are mainly used in the Internet of Things as well as in industrial applications.

  • Main Frequency 150MHz to 250MHz 512KB-2MB
  • Wide range of peripherals, including Neural Processing Units (NPUs) and DSPs
  • EdgeLock® Security Subsystem
  • Intelligent Peripherals

• MCX A Series, primarily for products where optimizing cost and time-to-market are key considerations.

  • Mains frequency 48 MHz - 180 MHz, 32KB - 1MB
  • Built-in timer, low pin count, single pin power supply
  • For cost-constrained applications

• MCX W SeriesThe product is a low-power wireless connectivity product with multi-protocol support.

  • 32MHz - 96MHz
  • Multi-Protocol Wireless Devices
  • Low Power BLE, Thread and Zigbee RF Devices for Industrial IoT & Matter Applications
  • On-chip integration reduces external BOM

• MCX L SeriesThe product is designed for ultra-low-power applications.

  • 50Mhz - 100 MHz with optional 50% multiplier
  • Very low power consumption and leakage
  • For applications with low power consumption requirements

• MCX C SeriesThe product is designed for ultra-low-power applications.

  • List item 48MHz，32KB–256KB
  • Easy-to-use peripherals
  • Cost-effective design for entry-level applications

I take a look at the block diagram of the MCXN947, as shown below, and the required components directly below

• CPU0 and CPU1 are both Cortexm33 cores.ARMv8-M architecture, 150 MHZ, though Core0's core supports more peripheral components, with support for DSPs, FPUs, DSPs, ETMs, and TrustZone, and coprocessor interfaces.
• 2MB internal FLash 512KB SRAM
• Supports system components, security components, debug components, communication components, simulation components, and timers components.

2. MCXN94 Memory Mapping

The memory of the MCXN994 is described in the figure below:




Note: The above space security and non-security spaces overlap.

• 0x0 - 0x001FFFFF: internal Flash address, 2MB size, divided into two banks, can be configured, each bank is 1MB, look at the above figure can see that, at present, each Program Flash is 1MB, N947 is 2MB, N946 is 1MB, you can look at the datasheet.

• 0x08000000 -0xFFFFFFF: FlexSPI peripheral, can be connected to Norflash, store code, up to 128MB, overlap with 0x80000000 peripheral address.

• 0x10000000 - 0x 101FFFFF: internal Flash address, 2MB size, divided into two banks, configurable, each bank is 1MB, overlapping with 0x0 above.

• 0x13000000 - 1303FFFF: Address of ROM Code

• 0x14000000 - 0x14017FFF: RAMX, above the code bus, suitable for code.

• 0x18000000 - 0x1FFFFFFF: FlexSPI peripheral, connects to Norflash, stores code, up to 128MB, overlaps with 0x90000000 peripheral address.

• 0x20000000 0x20007FFF : RAMA - RAMH address, RAM, can be used to store core1 code, as well as a portion of the shared space.

  • RAMA is relatively special, is divided into 4 banks, each bank 8K, can be used as retaintion for data in low-power scenarios, each bank is independently programmed power control , does not support ECC
  • All other banks have independent power switches that can be switched on and off as needed, and RAMG and RAMH serve as ECC data space

The following figure shows the setup of the RAM space configuration ECC, the

• You can see that RAMX and RAMB use RAMH for ECC data space, and by default these two checksums are on, so RAMH is not accessible as data
• RAMC, D, E, F use RAMG for ECC data checksums
• RAMA No ECC data checksum

The following figure shows the memory space distribution for core0 and core1 respectively:
Flash: 768KB FLash
RAM0: 304KB of RAM space
RAM1: 104KB of RAM space to hold code for core1
RAM3: Shared Space Code

Cache section:

• From the memory map address, you can see the cache portion of the address, the flash portion is the only one that has cache, the RAM portion is not cached.
• There are two kinds of cache, one is LPCAC, a low-power cahce for all flash addresses (including internal flash + flex spi flash), the size of 16KB, SYSCON LPCAC Control (LPCAC_CTRL) register can be configured for this cache, as shown in the first picture below
• One is CACHE64, only for the address range of FlexSPI, the size of 16KB, CACHE64_POLSE register can be configured cache attributes, as shown in the second figure below

The peripheral resources corresponding to the CPU model are shown below:

3. mcxn94 startup mode

There are only two types of boot methods: Internal Flash Boot and ISP Boot, which are determined by the ISPMODE (P06) pin.

• Booting from flash will look for a valid Image, if you enable Recover Image Flash, it will look for it in Recover ImageFlash, if it can't be found, it will enter ISP mode.
• From ISP Boot, can UART/IIC/SPI/USB support download code
  
  For ISP downloads, the configuration pins can determine the download mode or disable the ISP mode.
  
  

3.1 boot device

boot device: from internal flash boot, external Flash FlexSPI NorFlash boot (offset is 0x1000), SPI Flash Nor Recovery Boot, secondbootloader Boot。

Based on the BOOT SRC it can be decided whether to boot from internal flash or external flash.

• Internal flash boot
• External FlexSPI Flashboot
• SPI 1bit Nor Recovery boot
• Second bootloade rboot

3.2 Internal Flash Boot

When the internal flash is booting, you need to pay attention to theImage In the case of the header, NXP utilized a free position in the interrupt vector table and then did some vendor-defined operations.

• CM4 gets the interrupt vector table, the first SP pointer, the second is the entry function, and the process checks the legitimacy of the SP, such as an address belonging to RAM.
• 0x20, 24, 28, and 0x34 are free locations for customized operations.
• 0x24 is used to indicate the length of the current Image, including the length of the signature, which is only available if the Load is executed on RAM.
• 0x28 ImageType, and Image version information
• 0x28 The signature type, then the offset position of the certificate header, or the crc checksum value if it is a CRC signature type
• 0x34 Specifies the XIP type, or Image execution address if it is loaded to RAM.
  
  

The internal Flash boot process is shown in the following figure:

• Dual ImageBoot support, depending on Image Header at 0x24 for processing version
• Detect Image list information, FLASH_REMAP_SIZE specifies the size of the second image, if the size is 0, then there is no more than one image
• run bootloader specifies the boot image, and if so, the specified image index is run.
• If not, did boot fail before, if not, the image index is 0.
• If yes, is the previous image index 1, if yes, image boot failed
• If yes, the image index is 1 and the image process continues
• Determine if image exists, if not boot fails, return to main boot process.
• If present, the image header is loaded into ram space, whether or not secure boot is enabled, the
• If yes, perform the secure boot process
• If not, then check the image type, and if it is a non-XIP image, then you need to copy the image to the destination ram address
• If it is a crc image, do a crc check, the check is valid and the SP PC is valid, then jump to the user program
• If PC and SP are invalid, the second image exists, and it is currently the first image, the setup boot fails, triggering a system reset and another boot flow
• In the case of a secure boot, authorization is verified using the ECDSA security algorithm, the
• If the image authorization is unsuccessful, determine if there is a second image and proceed to the next boot process
• If the authorization is successful, proceed with the image CMAC update process
• Then determine whether SP and PC are valid, if so, determine whether TZM data exists, if so, execute TZM data configuration
• If it doesn't exist, it jumps directly to the app.

A dual Image process operation can be generated by setting FLASH_REMAP_SIZE.

• If FLASH_REMAP_SIZE is set, the 0 address is mapped to the address of bank1, and then the boot rom can be booted.
• Set FLASH_REMAP_SIZE via CMPA or eFUSE.
  
  
  

3.3 external Flash Boot

External Flash from FlexSPi Flashboot, need to have FCB information at 0x400, 512Byte, as Flash configuration parameter.


The boot process is as follows:

1. Entering the internal flash memory processing, detecting valid image information, and preparing imgae list information.
2. The bootloader API runs a specific boot image, and if so, sets the image index.
3. If the corresponding image exists, then proceed to the image detection process
4. If no bootloader API is specified for Image, determine if the image boot failed previously
5. If not, set the stock image index to 0.
6. If yes, determine that the previous image index is 0, then set the current image index to 1 for the image boot process
7. If the image corresponding to the specified Image index does not exist, determine whether to enter the recovery reboot process.
8. Otherwise, the boot fails, triggering a reboot.
9. The image boot process loads the image header information and determines whether it is a secure boot.
10. If not, then check the image type, and if it is not XIP, then move the Image to the corresponding sram.
11. Then the CRC as well as the SP PC is performed, as in the above process.
    

4、mcxn94 Code Download

I use frdmmcxn947 development board, directly through the MCU_XPRESS, downlaod on it.

Select core to debug.

Debugging Interface:

Actual board

5. Reference

1、NXP new series products MCX series products
2. MCXNx4xRM-MCXN947 User's Reference Manual